1) Field of the Invention
The present invention relates to an information processing device such as a microprocessor or a digital signal processor having a cache memory or a memory, and an information processing method. More particularly, this invention relates to a technology preferably applied to data reading and data writing from and to a cache memory or other memories in an image processor or the like.
2) Description of the Related Art
In the microprocessor, or the digital signal processor (hereinafter, called simply as an information processing device), data to be processed is read from the cache memory or the memory such as a random access memory (RAM) and a read-only memory (ROM) for processing at data processing. After completion of the processing, data as a result of the processing is written in the cache memory or the memory. In such a case, the address and the size of data to be processed are specified, and the data which starts from the specified address is read. Then, the data is written in an area for the specified size starting from the specified address.
A configuration for data reading or data writing in a conventional information processing device will be described with reference to an example of a cache memory which has a read or write size in a range between a maximum 64-bit width and a minimum 8-bit one, and a capacity of 8 kilobytes according to a direct map method. Here, read and write bus widths are assumed to be 8 bytes, that is, 64 bits.
FIG. 1 is a block diagram showing a configuration for data reading or data writing in such a conventional cache memory. As shown in FIG. 1, target base addresses and offsets to write data are stored into a first register 11 (register 1) and a second register 12 (register 2), respectively, in the conventional information processing device at data writing. Further, the size of the write data is stored into a third register 13 (register 3).
The base addresses and the offsets stored in the first register 11 and the second register 12 are added in an address adder 14, whereby an address of [12:0] representing a target address for write is generated. Here, in the present specification, [a:b] represents data having a width of (a−b+1) bits, from (b+1)th bit to (a+1)th bit where a and b are integers equal to or larger than zero. In the address of [12:0] output from the address adder 14, low-order 3 bits represented by [2:0] are supplied to a write control circuit 15, and the remaining 10 bits of [12:3], that is, the 10 bits of the fourth bit to the 13th bit are supplied to a memory 16.
Data sizes are supplied from the third register 13 into the write control circuit 15, and write control signals of [7:0] are generated based on the low-order bits in the address of [2:0] supplied from the address adder 14. One-bit write control signals of [0] to [7] corresponding to individual eight memory areas with a width of 8 bits in the memory 16 are supplied to the memory areas, respectively, and data to be written in the memory (“memory write data”) 17 are written in the memory areas specified by the respective control signals. Here, when c is an integer equal to or larger than zero, [c] represents data of the (c+1)th bit from the least significant bit (LSB).
The address of [12:3] is, at data reading, supplied to the memory 16 from the address adder 14 in a similar manner to that at the data writing, based on the base addresses and the offsets respectively stored in the first register 11 and the second register 12. Further, data of a predetermined size, for example, 32 bits in the case Word unit, and 64 bits in the case Double word unit, are read from the memory 16 as data read from the memory (“memory read data”) 18.
Incidentally, when the addresses are aligned, at data writing or data reading, differently from those according to the sizes of data to be written in the memory 16 or the sizes of data to be read from the memory 16, data reading or writing can not be executed in hardware of the conventional information processing device. Therefore, exception is detected to cause the processing to be interrupted. Alternatively, the addresses are required in software to be aligned according to the sizes of the data so that no interruption of the processing occurs.
When addresses are aligned according to the size of the specified data as shown in FIG. 2, the values of any bits are not cared when the specified size is Byte in the low-order bits in the address of [2:0]. Further, only the value of the bit of [0] is required to be zero when the specified size is Half word. Moreover, the values of bits of [1] and [0] are required to be zero when the specified size is Word. In addition, the values of all the bits are required to be zero when the specified size is Double word. Therefore, the case where the addresses are aligned differently from those according to the size of the specified data indicates a case where the conditions shown in FIG. 2 are not met.
For example, as shown in FIG. 3, when the address of data to be read or written is 32′h00000015 and the specified data size is of 8 bytes, the value of a bit of [2] in the address is 1, that of a bit of [1] is zero, and that of a bit of [0] is 1. The above states do not meet the conditions that are required as shown in FIG. 2 when the data size is of 8 bytes. Accordingly, the example shown in FIG. 3 signifies that the addresses are not aligned with respect to the data size of 8 bytes. In such a case, the 8-byte addresses starting from an address of 32′h00000015 cross over an 8-byte boundary set in the memory.
In the example in FIG. 3, the 8-byte boundary includes, for example, a boundary between 32′h00000007 and 32′h00000008, that between 32′h0000000F and 32′h00000010, and that between 32′h00000017 and 32′h00000018.
Generally, addresses for data reading or data writing are apparent only at execution of software. Therefore, the conventional information processing device has had a problem that longer processing time for data reading or data writing is required when the addresses of data to be read or written are not aligned as described above, because reading or writing of data with a 1-byte size as a minimum unit is required to be executed eight times when the data size is of 8 bytes.